1. Technical Field
The present invention relates to test runs and repairs for memories, and more specifically, to multiple on-chip test runs and repairs for memories.
2. Related Art
Conventional testing of a memory chip involves a plurality of test runs during each of which the memory chip is tested under a different condition (voltage, temperature, etc.) The resulting test-run repair solution for each test run is collected and stored off-line (i.e., outside the memory chip). Once all test-run repair solutions for all test runs have been collected, they are compiled off-chip into a final repair solution which is implemented by programming the fuses on the memory chip. This testing process wastes tester time because the tester has to wait until the final repair solution has been compiled off-chip before proceeding to implementing the final repair solution.
As a result, a design of a memory chip that allows multiple on-chip test runs and repairs is needed. A method is also needed for performing multiple on-chip test runs and repairs for the memory chip.